A powerful new RISC-V microcontroller with mostly open RTL
Baochip-1x raises the bar on inspectable hardware, bringing you a system-on-chip (SoC) that you can check from the silicon all the way to the software. Not only is the entire bootloader open-source and NDA-free, most of the design source for the compute logic is open and NDA-free. To top it off, the chip comes in a package specifically designed to facilitate Infra-Red, In-situ (IRIS) inspection - a non-destructive way to look at the silicon and confirm you’ve got the right chip based on the pattern of transistors printed on the silicon itself.
You can get your hands on a Baochip-1x by pre-ordering the Dabao Evaluation Board in this campaign: a Baochip-1x mounted on a cost-optimized 2-layer board, targeted at entry-level embedded developers and hobbyists.
Baochip-1x is positioned as a "general-purpose" microcontroller, yet it shares features normally found exclusively in NDA-only hardware secure elements: multiple cryptography accelerators, key stores, one-way counters, true random number generation, and hardware attack countermeasures such as glitch sensors and a security mesh.
At Baochip, we believe great security should be standard and open. Access to top-notch hardware security shouldn’t be only for the privileged elite, the well-connected, or big corporations: it’s long overdue for everyday product specs to assume these basic primitives as building blocks, so that we can build better, more secure products as a community.
Can something be both secure and fun to hack? We think so.
A core use case of embedded microcontrollers is interacting with real-world devices - sensors, LED strips, various bus standards. The Dabao’s Baochip-1x features the "BIO", a 700 MHz, quad-core PicoRV-powered I/O coprocessor that enables a wide range of I/O applications.
Each PicoRV core in the BIO has a dedicated 4 kiB RAM for code and data, and features register-mapped GPIOs, inter-processor communication, and event handling thanks to custom hardware extensions implemented over the base RV32-EMC architecture. Not only can the BIO bit-bang an LED strip, it can also render simple animations, freeing the main CPU for other applications, or simply being shut down for power savings.
I’ve really enjoyed hacking on the BIO, and I hope you do, too. The possibilities feel limitless, and if you’re a baremetal, assembly-language type of hacker, you’re going to love playing with the BIO. The BIO has a really solid "road feel" and because it’s open source, you can also check your code with RTL simulations.
Unlike comparable I/O cores on other microcontrollers, the BIO is 100% open source and patent-free - so anyone can make chips using the BIO IP. You’re not locked into buying Baochip silicon; in fact we have published a demo of the BIO RTL targeting an Arty A7 FPGA board.
Open architectures mean you can own your ideas - you are empowered to build your own versions of the hardware that runs them. You don’t have to trust us to be the corporate stewards of your chips. If you’re unhappy with our direction, we encourage you to fork the code and build your own, better version!
Baochip changes the status quo by making evidence-based trust a core principle of its design. You, the user, will have reasons to trust the Dabao’s Baochip-1x CPU based on scientific evidence that is observable without access to a million-dollar microscope.
See the actual transistors inside Baochip using a technique called IRIS: all you need is a slightly modified CMOS microscope camera and LED illuminator. Learn more about IRIS and how to modify a camera.
In addition to being able to see the physical transistors, you can inspect the logical design behind the active compute portions of the chip by browsing the RTL in the Baochip-1x GitHub repository.
And of course, all of the code that comes on the chip in the form of its bootloader and OS is 100% open source and inspectable. Extra attention was given to the bootloader to ensure that anyone can reproduce the actual binary image using a GUIX toolchain.
Thanks to this design principle, Baochip-1x is well-suited as a hardware development framework for security-critical applications such as password managers, authenticators, and other high-assurance applications — or just bringing security to your everyday IoT project!
Here’s how the Dabao stacks up against a variety of other popular small development boards.
| Dabao | Raspberry Pi Pico 2 [1] | Espressif ESP32-DevKitC [2] | Seeed XIAO ESP32C3 [3] | Teensy 4.1 [4] | Arduino Nano 33 IoT [5] | Adafruit Feather M4 Express [6] | BBC micro:bit v2 [7] | |
|---|---|---|---|---|---|---|---|---|
| Manufacturer | Baochip | Raspberry Pi Ltd | Espressif Systems | Seeed Studio | PJRC | Arduino | Adafruit | Micro:bit Educational Foundation |
| MCU/SoC | Baochip-1x (single-core Vexriscv) | RP2350 (dual-core Cortex-M33) | ESP32 (dual-core Xtensa LX6) | ESP32-C3 (single-core RISC-V) | NXP iMXRT1062 (Cortex-M7) | SAMD21 (Cortex-M0+) | SAMD51 (Cortex-M4F) | nRF52833 (Cortex-M4F) |
| Clock Speed | 350 MHz | 150 MHz | 240 MHz | 160 MHz | 600 MHz | 48 MHz | 120 MHz | 64 MHz |
| I/O Coprocessor | BIO (4x PicoRV @ 700MHz) | 2× PIO blocks (8 state machines) | 2× ULP cores (RISC-V / FSM) | 1× ULP core (RISC-V) | FlexIO (flexible I/O emulation) | SERCOM (configurable serial blocks) | SERCOM (configurable serial blocks) | None |
| Hardware Security | Signed boot, TRNG, key store, one-way counters, HW accels: RSA, ECC, ECDSA, X25519, SHA256/512, SHA3, Blake2/3, AES; secure mesh, glitch sensors, ECC-protected RAM | TrustZone, signed boot, OTP key store, HW SHA-256, TRNG | eFuse secure boot + AES flash encryption, HW RNG | eFuse secure boot + AES flash encryption, HW RNG | HAB secure boot, AES-256 encrypted XIP (lockable variant) | NVM read-back protection only | NVM read-back protection only | Read-back protection only; no HW crypto |
| IRIS inspectable | Yes | No | No | No | No | No | No | No |
| Open Bootloader | Yes | Yes | No | No | No | No | No | No |
| Open RTL | Mostly open | No | No | No | No | No | No | No |
| Memory protection | MMU | MPU + trust zone | MPU-like | PMP | MPU | MPU | MPU | MPU |
| Swap memory support | Yes (w/Xous and external PSRAM chip) | No | No | No | No | No | No | No |
| Rust-native | Yes | No | No | No | No | No | No | No |
| RAM | 2048 KB + 256KB I/O buffers | 520 KB | 520 KB | 400 KB | 1 MB | 256 KB | 192 KB | 128 KB |
| Flash | 4 MB (Internal RRAM) | 4 MB | 4 MB | 4 MB | 8 MB + SD slot | 1 MB | 512k internal + 2 MB external | 512 KB internal |
| Flash Interface | Internal (XIP up to ~1200 MB/s) | QSPI (up to ~56 MB/s XIP) | QSPI (~40 MB/s typical) | QSPI (~40 MB/s typical) | FlexSPI octal/quad (~100 MB/s XIP) | Internal NVM (XIP est ~200 MB/s) | Internal NVM (XIP est ~400 MB/s) | Internal NVM (XIP est 20-40 MB/s) |
| GPIO Pins | 20 | 26 | 34 | 11 | 55 | 22 | 20 | 5 large / 19 total |
| Wireless | None | None (W variant adds Wi-Fi/BT) | Wi-Fi + Bluetooth 4.2 | Wi-Fi + Bluetooth 5 | None (add-on available) | Wi-Fi + Bluetooth | None (Wing ecosystem) | Bluetooth 5.0 + 2.4 GHz |
| USB | USB-C (USB2.0 HS device) | Micro-USB (native) | Micro-USB (via CP2102) | USB-C (native) | USB-C (native, device+host) | Micro-USB | Micro-USB | Micro-USB |
| Best For | Security, High-assurance & General-purpose | General-purpose, MicroPython/C++ | IoT projects, wireless connectivity | Tiny wireless nodes, wearables | Audio DSP, high-speed data, USB MIDI/HID | Arduino ecosystem, rapid prototyping | CircuitPython, modular add-on Wings | Education, kids, classroom coding |
| Price (approx.) | $9.50 | $5–$7 | $8–$12 | $5–$7 | $30–$35 | $20–$25 | $20–$24 | $15–$18 |
[1]: Pico 2 datasheet + RP2350 datasheet + Bootrom source
[2]: DevKitC user guide + ESP32 datasheet + ESP32 TRM
[3]: XIAO ESP32C3 wiki + ESP32-C3 datasheet
[4]: Teensy 4.1 product page + iMXRT1062 datasheet + iMXRT1062 reference manual
[5]: Nano 33 IoT docs + SAMD21 datasheet
[6]: Feather M4 guide + SAMD51 datasheet
[7]: micro:bit hardware spec + nRF52833 product spec
Dabao backers will receive the dabao evaluation board in antistatic packaging.
Baochip-1x has gone through an engineering qualification lot and been distributed in limited quantities to alpha developers. As such, the design risk is deemed to be low and chip yields so far seem acceptable.
To fully understand the manufacturing flow, it’s important to establish the context of Baochip. Baochip buys its wafers through a company called Crossbar. They are the "host" company that paid for the mask set; Baochip is a "hitchhiker" on their mask in the sense that Crossbar allowed us to put our CPU core on their chip, and through chip probe-time fusing their features are turned off. Thus our chips share the exact same mask, but you wouldn’t guess that we’re the same die unless I told you this. And to be clear, our version has some "dead silicon" that can’t be used because it’s been disabled - and for what it’s worth, this is a standard industry practice to use one mask to create multiple product "views" on the same chip by disabling cores or features.
There are two revisions of the die, an -A0 stepping and an -A1 stepping. From the standpoint of Baochip, the revisions are transparent: the firmware is designed to run on both identically. The -A1 version has some critical fixes for the Crossbar variant, but since their CPU is turned off on our version, these fixes don’t affect us. Thus for Baochip variants, the main difference is that the -A1 stepping hardens access to the RRAM configuration register. The main purpose of the hardening is that in case the kernel or bootloader is breached and an arbitrary-write primitive has been achieved, an attacker would be unable to modify the access control bits on the RRAM. However, in practice, by the time an attacker has an arbitrary-write primitive in the kernel or bootloader, there are numerous other more powerful exploits available, so this stepping effectively seals off only one bad outcome out of many in the case of a kernel bug.
The -A1 stepping may not be in full production until much later in 2026, so to pull in the schedule for this campaign, we will be shipping mostly -A0 stepping chips to end users.
With that in mind, here is the manufacturing timeline:
We will be relying on Mouser Electronics, Crowd Supply’s fulfillment partner, to handle the global shipment of devices to backers. For more information about shipping, please see Crowd Supply’s Ordering, Paying, and Shipping guide and the International shipping section of their Fulfillment & Logistics guide.
Global instability is the most significant risk to delivery. The design itself is vetted and working, and the supply chain is set up to pump out chips - just need to know how many to build. The following outcomes could greatly impact the timing of delivery:
Rationale for development and architecture details on youtube here: https://m.youtube.com/watch?v=DaWkfSmIgRs
Absolutely looking forward to this. The Risks & Challenges section is a bit disheartening but necessary.