Nope. Very common. Making a FIFO also randomly content-addressable adds a lot to the complexity, and only code too unoptimised to care about loads a value within half a dozen instructions of storing it -- just use it directly from the register you stored it from.

The CH32V003 is a nice RISC-V chip at a great price, and deservedly popular, but there is in fact an Arm chip in the same space, the Cortex-M0+ Puya PY32F002A, which has the same MHz but a little more RAM (3k) and flash (20k).

Being Chinese there has been some suggestion that they haven't actually paid for the CM0 core, but it's supported in Keil and I think listed somewhere on the main Arm site too, which tends to rule that out.

(WCH has already introduced successors to the CH32V003 with more RAM and flash at the same $0.10 price -- and even the CH570D with 96 MHz, 12k RAM, 240k flash, USB, and a 2.4 GHz packet radio -- but they are not as widely available yet)

SiFive was founded by academics who had successfully taped out a number of processor chips. They subsequently hired many experienced industry CPU designers from Arm, Intel, AMD and others.

> the future of SiFive is unclear

What is that supposed to mean? The future of Intel is unclear. The future of Arm is unclear. The future of Tesla is unclear. The future of Boeing is unclear. That's just life in a highly competitive industry.

> Choosing another language is pretty much impossible, unless you translate it to either SystemVerilog or VHDL.

?? Which of course is exactly what Chisel has always done. Do you even know anything about it?

> If you do that, then it is hard to justify using another language instead of writing directly in SystemVerilog or VHDL.

No it is not.

Chisel enables much more abstraction than Verilog, enabling you to design not just a single CPU core but a family with very different characteristics. Diplomacy simply has no analog in the Verilog world.

Chisel, FIRRTL, CIRCT enable the same kind of optimisations on RTL as GCC or LLVM do for C code. In fact CIRCT is built on LLVM. You can emit Verilog that is optimised for different hardware technologies, including different PDKs, or FPGA vs ASIC, in a way that is completely impossible with Verilog.

I suppose everything that isn't a toy implementation has a store queue.

Even the U54 Core Complex (later U54-MC) manual from August 2018 states in Section 3.4 "Stores are pipelined and commit on cycles where the data memory system is otherwise idle. Loads to addresses currently in the store pipeline result in a five-cycle penalty."

It probably inherited this from Rocket.

SiFive, the leading RISC-V IP vendor, with cores available (at the moment) up to around Cortex-X2 level, has been taping out chips from Chisel since 2016.

Their first chip, a 32 bit microcontroller, ran at 320 MHz on TSC 180nm, while the comparable Arm Cortex-M4 was typically limited to 180 MHz on the same process node.

The EIC7700X, using SiFive P550 cores, given nice solid Core 2 Quad (or Raspbery Pi 4) performance.

SiFive's X280 cores are being used in rad-hard Microchip chips for NASA.

This is not exactly "academic" or "hobby".