I wonder if this will get RISC-V adoption on the roadmap of competitors. We had a thread in the last 24 hours over how slow as molasses it is, but honestly x86 isn’t the way to go. I like that the AMD x64 literature tries to push down on the legacy cruft but some of it is evident in the ISA which is harder to ignore, like default behaviours of registers and other things that are left over for backwards compat and as such everything around it suffers in a thousand broken windows sort of way.
nb I haven’t delved too deep into RISCV but I am under a general impression it did away with all this. My concern is the layers that are added will turn it into a CISCV over time.