It's often a requirement for bare metal embedded development (too heavy in terms of memory), so it's basically unavoidable. Non-standard languages are very common for this kind of thing, just look at the linux-flavoured C.

Signal Priority only works well if the arrival time of the bus can be predicted some time before arrival at the signal (~30 seconds is a number I've heard a few times). As bus stopping times are highly unpredictable, a lower number of bus stops makes signal priority work much better (and far-side bus stops).

Furthermore signal priority and own lanes are almost always beaten by good circulation planning, reducing the number of traffic lights and cars on the route of the bus.

Certainly not with hydrogen directly. It might be involved in the production chain, but it's such a pain. If it's at all possible to electrify, that'll very likely win.

For flights, a combination of batteries for smaller, regional planes starting with "islands hoppers" now and SAF from either Biofuel or produced from Electricity (with Hydrogen as an intermediate step). Although I think that we might first see moves to reduce the 2x non CO2 Climate Impacts which can be much cheaper to tackle (such as Contrails).

For maritime applications, batteries when regularly near ports, probably hybrids with methanol for cross-ocean passage far away from coasts.

It's still the lingua-franca of ASIC/FPGA/Simulation, especially for scripting the tools.

I think it's slowly being replaced there by Python, but it's very slow.

The Hazard 3 is basically a hobby project of Luke Wren, a Raspberry Pi Employee. He's contiuing to evolve it further, but I don't think it's ready for a full replacement of the Cortex-M yet, especially in regards to the Security Features.

The source code is all from Luke Wren and I don't think other cores use the source code directly, but improvements to test harnesses or general implementation patterns as well as better software support help other cores: https://github.com/Wren6991/Hazard3

For the SoCs I would expect to see an off-the-shelf Risc-V core (certainly no Hazard3 as the main CPU), but we'll see.